Engineer · Researcher · Educator

Dr. Anirban Chakraborty

CPU Microcode Engineer at Intel · Ph.D. in Electrical Engineering · Editor-in-Chief, ASIR.

Start herePart I · 1/66

The Computing Stack

Computer architecture is the study of how the hardware that runs software is organized. This opening chapter introduces the field and the vocabulary the rest of the book uses. The discussion moves from purpose…

Architectural Foundations61 min read

Recent commits

  • 83db158chore(secrets): reseal .env.local.enc
  • fa8a1fefix(photography): correct the Field Manual's chargers and add the PH-10
  • 10fb286feat(content): move the field manual to the Lexar cards
Scroll
The Shelf

Written to be read in order

Three books, each starting from nothing and assuming no background beyond school mathematics, longest first. The Parts below are the reading order, not a menu.

The Hardware Interview

The same architecture, organized the way an interview is organized.

≈ 42.7 h of reading

  1. Part IFoundations6
  2. Part IIThe Core7
  3. Part IIIOut-of-Order Execution5
  4. Part IVPhysical Design and Silicon10
  5. Part VSystems, Accelerators and Interconnect3
  6. Part VIThe Room5

Computer Architecture

From first principles to the out-of-order engines in shipping processors.

≈ 32.3 h of reading

  1. Part IArchitectural Foundations12
  2. Part IIInstruction Set Architectures12
  3. Part IIISingle-Cycle, Multi-Cycle, and Pipelined CPUs11
  4. Part IVMemory Hierarchy13
  5. Part VAdvanced ILP and Out-of-Order Execution18

Post-Quantum Cryptography from First Principles

The mathematics behind ML-KEM and ML-DSA, built from nothing.

≈ 7 h of reading

  1. Front matterBefore you start1
  2. Chapter 1Finite Fields and Polynomial Rings10
  3. Chapter 2Why Post-Quantum Cryptography?10
  4. Chapter 3Lattices and Learning With Errors11
  5. Chapter 4Ring-LWE, Module-LWE, and the Number Theoretic Transform11
  6. Chapter 5ML-KEM11
  7. Chapter 6ML-DSA11
  8. Chapter 7Modular Reduction and the Keccak Sponge10
  9. ReferenceNotation and further reading2
82

Hours of reading across three books

7

Peer-reviewed papers

4+

Years in industry

Featured ProjectActive

Yantra — CPU Design from Scratch

A ground-up CPU RTL design in SystemVerilog — from combinational building blocks through a fully pipelined processor, with open-source tooling.

Build log

terminal
  • 83db158 chore(secrets): reseal .env.local.enc
  • fa8a1fe fix(photography): correct the Field Manual's chargers and add the PH-10
  • 10fb286 feat(content): move the field manual to the Lexar cards
  • db75b6b feat(content): add the 180-600 and its accessories to the field manual
  • 3cb8732 fix(build): raise the static generation timeout for the long chapters

Read from the repository when this page was built. The site is static, so this is the state of the source at the last deploy rather than a live feed, and the repository itself is private.

About

From Silicon to Systems

CPU Microcode Engineer at Intel with a Ph.D. in Electrical Engineering. Work spans microcode, RTL design, and hardware architectures for Error Correction Coding. Editor in Chief at Applied Science and Innovative Research, editorial board member at the Journal of Education and Culture Studies, and seven peer-reviewed papers.

Learn more about me
Get in Touch

Let's Connect

Collaboration, research, speaking, or just a hello — pick the channel that suits you.

Tools of the trade

SystemVerilogVHDLVerilogPythonCMATLABSynopsys DCPrimeTimeCadence VirtuosoModelSimXilinx VivadoIntel QuartusCadence JasperGoldVerdiRTL DesignPhysical DesignFPGAUVMTclLinuxSystemVerilogVHDLVerilogPythonCMATLABSynopsys DCPrimeTimeCadence VirtuosoModelSimXilinx VivadoIntel QuartusCadence JasperGoldVerdiRTL DesignPhysical DesignFPGAUVMTclLinux