Engineer · Researcher · Educator
I'm a CPU Microcode Engineer at Intel Corporation, where I work on the microcode of the CPU cores for current and next-generation processors. Before that, I worked as a Logic Design Engineer in the same company, developing the Resource Controller IP and designing registers for Intel SoC platforms that included power and performance optimizations.
I hold a Ph.D. in Electrical Engineering from the University of North Texas, where my research focused on reconfigurable computing architectures, error correcting codes, and RTL design using 45nm and 28nm CMOS technologies. I've published 7 peer-reviewed papers and serve on the editorial boards of two academic journals.
Outside of work, I write about hardware design, computer architecture, and the intersection of EDA tooling with modern engineering practice. The best engineers are the ones who can reason across abstraction layers — from transistors to system architecture.
CPU Microcode Engineer
- Developing and validating CPU microcode for current and next-generation Intel processors.
- Collaborating with architecture, design, and validation teams to resolve silicon issues.
- Driving microcode optimizations to improve performance and power efficiency.
Editorial Board Member
- Reviewing and evaluating submitted manuscripts in electrical and computer science.
- Providing editorial guidance on publication standards and technical rigor.
Editor in Chief
- Leading editorial direction and overseeing the peer-review process.
- Making final publication decisions and maintaining journal quality standards.
Logic Design Engineer
- Worked on Resource Controller IP Development for Intel SoCs.
- Designed and implemented Registers for Intel SOC platforms.
- Worked on improving the Dynamic Clock Gating Efficiency (DCGE).
- Performed RTL design, synthesis, and timing closure using industry-standard EDA tools.
Graduate Research & Teaching Assistant
- Served as teaching assistant for courses in Digital design using VHDL and VLSI.
Seacom Engineering College
West Bengal, IndiaGuest Faculty
- Taught undergraduate courses on Electrical Machines and related subjects.
- Developed course materials and conducted laboratory sessions.
Ph.D. in Electrical Engineering
GPA: 3.75 / 4.00 · IEEE-HKN (Eta Kappa Nu) Honor Society Member
- Research focus: Reconfigurable computing, error correcting codes.
- Published 7 peer-reviewed papers across journals and conferences.
- Designed and validated circuits using 45nm and 28nm CMOS process technologies.
M.Eng. in Electrical Engineering
Aggregate: 77.94%
- Specialization in Electrical Machines and Power Systems.
- Coursework in advanced control systems and power electronics.
B.Tech. in Electrical Engineering
DGPA: 8.63 / 10
- Affiliated to West Bengal University of Technology (WBUT).
- Strong foundation in electrical circuits, electronics, and control systems.
Arm
Johns Hopkins University
7 peer-reviewed publications · View dissertation
Evolution of the Internet of Things and Fundamentals of Human-Machine Interaction
Area and Power analysis of a Scalable Primitive Polynomial computation circuit over the field GF(2)
Power, Performance, and Area Analysis of Hardware Design Techniques for GF(2k) Greatest Common Divisor computation
What I Work With
Hardware description languages, EDA tools, programming languages, and the research domains they touch.
Category
HDL & Hardware Languages
- VHDL
- SystemVerilog
- Verilog
- UVM
- SystemC
- SPICE
Category
EDA & CAD Tools
- Synopsys Design Compiler
- Synopsys PrimeTime
- Cadence Virtuoso
- Xilinx Vivado
- Intel Quartus
- ModelSim
- Jaspergold
- Verdi
- Synopsys VCS
Category
Programming Languages
- Python
- C
- R
- MATLAB
- Tcl
- Bash
- SQL
- TypeScript
Category
Design & Verification
- RTL Design
- Physical Design
- Logic Synthesis
- Timing Analysis
- Formal Verification
- Gate-Level Simulation
- 45nm CMOS
- 28nm CMOS
Category
Domains & Research
- CPU Microarchitecture
- Reconfigurable Computing
- Error Correcting Codes
- FPGA Design
- Digital Signal Processing
- ASIC Design
- Low-Power Design
- SOC Architecture
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